1. Basic Structure of Embedded Microprocessors

(1) An embedded hardware system generally consists of an embedded microprocessor, memory, and input/output components.

(2) The embedded microprocessor is the core of the embedded hardware system and typically consists of three main parts: control unit, arithmetic logic unit, and registers:

A. Control Unit: Responsible for basic operations such as fetching instructions, decoding, and retrieving data, and sending major control commands.

B. Arithmetic Logic Unit: Primarily processes numerical data and performs logical operations.

C. Registers: Used for temporarily storing data.

2. Classification of Embedded Microprocessors (Based on Purpose)

(1) Embedded Microcontroller (MCU): Also known as a microcontroller, it generally has rich on-chip peripheral resources and is suitable for control applications. Its greatest feature is its compactness, low power consumption, low cost, and high reliability. Currently, it accounts for about 70% of the market share.

(2) Embedded Microprocessor (EMPU): Also known as a single-board computer, it evolved from CPUs in general-purpose computers and is characterized by having a processor with 32-bit or more, offering high performance. Typically, embedded microprocessors integrate CPU, ROM, RAM, and I/O modules onto a single chip.

(3) Embedded DSP Processor (DSP): Specifically designed for signal processing, its system architecture and instruction algorithms are specially designed to achieve processing speeds 10 to 50 times faster than the fastest CPUs, with extensive applications in digital filtering, FFT, and spectral analysis.

(4) Embedded System on Chip (SOC): Aiming for the maximum integration of product systems, its greatest feature is the seamless integration of hardware and software, directly embedding the operating system’s code module within the microprocessor chip.

3. Structure and Characteristics of Typical Microprocessors

(1) 8-bit Microprocessor: Focused on the 8051, thoroughly understanding the working principles of 8-bit microcontrollers, peripheral control, memory distribution, addressing methods, and typical applications.

(2) 16-bit Microprocessor: A typical microprocessor can refer to MSP430; consult a book on MSP430’s structural principles and typical applications.

(3) 32-bit Microprocessor: A 32-bit processor uses a 32-bit address and data bus, with an address space reaching 2³² = 4GB. Currently, mainstream 32-bit embedded processor systems include ARM series, MIPS series, and PowerPC series. The ARM microprocessor architecture is recognized as the leading 32-bit embedded RISC processor structure in the embedded applications field. Given the current development trends, ARM has almost become synonymous with embedded applications.

4. Basic Concepts of Microcontroller Systems

(1) Composition of Microcontrollers: Central processing unit, memory, I/O devices.

(2) Memory: Physically consists of one or more integrated circuits with data input/output and storage functions, serving as device cache or storing fixed programs and data.

A. ROM (Read-Only Memory): Generally used to store fixed programs or data tables, retaining data even after power loss.

B. RAM (Random Access Memory): Used to temporarily store programs and data, intermediate calculation results, or as a stack, losing data upon power loss.

(3) I/O Ports: Channels for microcontrollers to communicate with the outside world, capable of detecting, judging, and processing various external signals (digital signals, analog signals, frequency signals), and controlling various external devices. Modern microcontroller I/O ports have integrated more features and functionalities, expanding and reusing I/O port functions, such as external interrupts, ADC detection, and PWM output.

(4) Output Levels: High-level voltage (output “1”) and low-level voltage (output “0”)

A. TTL Level: Positive logic, 5V is logical high, 0V is logical low, such as in microcontroller outputs.

B. RS232 Level: Negative logic, -12V is logical high, +12V is logical low, such as in PC outputs.

Note: Therefore, when communicating between microcontrollers and PCs, a MAX232 chip is needed for level conversion.

(5) Stack: A linear data structure with only one entry/exit point.

A. Stack Characteristics: Last In First Out (LIFO)

B. Stack Pointer: Indicates the position (address) of the stack top; when a push or pop operation occurs, the stack pointer changes accordingly.

C. Stack Operations: Push (PUSH) and Pop (POP).

D. Stack Types: “Growing Upward” stack, where the stack pointer increases by 1 with each push; “Growing Downward” stack, where the stack pointer decreases by 1 with each push.

E. Stack Applications: Used for subroutine calls and interrupt responses to protect the context; can also serve as a temporary data buffer.

F. Usage Notes: Issues with stack overflow, matching push and pop operations.

(6) Timer Counter: Essentially a counter. When used as a timer, it counts internal clock pulses of the microcontroller, while as a counter, it counts external input pulses. Its functions include:

A. Timing, scheduling, or delay control;

B. Pulse technology;

C. Measuring pulse width or frequency (capture function)

(7) Interrupts: Higher priority events interrupt lower priority time processes. Events causing interrupts are called interrupt sources. A microcontroller may support multiple interrupt sources, which can be divided into maskable and non-maskable interrupts, and not all of these interrupt sources are necessary for system operation; we can mask those that are not needed based on system requirements.

A. Interrupt Nesting: When a lower-level interrupt has not completed execution and a higher-priority interrupt occurs, the system switches to execute the high-level interrupt service routine, returning to execute the lower-level interrupt service routine after the high-level interrupt is handled.

B. Interrupt Response Time refers to the time taken from issuing an interrupt request to entering interrupt handling; Interrupt Handling Time refers to the time from the start of interrupt handling to its completion.

C. Interrupt Response Process:

a. Protecting Context: Saving the current address, accumulator ACC, and status register to the stack. b. Switching PC Pointer: Switching to the corresponding entry address based on the interrupt generated by different interrupt sources. c. Executing the Interrupt Service Routine. d. Restoring Context: Restoring the main program address, accumulator ACC, and status register from the stack. e. Interrupt Return: Returning from the interrupt to the main program and continuing execution.

D. Interrupt Entry Address: Each interrupt source is assigned a different interrupt entry address by the microcontroller, also known as an interrupt vector.

(8) Reset: An external circuit sends a reset signal to the microcontroller, causing the system to restart.

A. Actions When Reset Occurs:

a. The PC pointer starts executing from the initial position (most microcontrollers start from 0x0000). b. I/O ports are set to default states (high impedance or output low level). c. Some special control registers SFR are restored to default states. d. Ordinary RAM remains unchanged (if it is power-on reset, then it is random data).

B. Two Different Reset Startup Methods:

a. Cold Start: Also known as power-on reset, refers to applying power to the system from a power-off state to begin normal operation. b. Warm Start: Resetting the microcontroller with a reset signal while power is still on, causing the system to restart.

C. Two Types of Reset Circuits: High-level reset and low-level reset.

D. Cautions:

a. Ensure that the level state and duration of the reset signal meet system requirements. b. Avoid jitter in the reset signal.

(9) Clock Circuit: The microcontroller is a sequential circuit that requires a pulse circuit to function properly. The clock circuit acts as the heart of the microcontroller, controlling its working rhythm with each pulse (vibration beat). If the oscillation is slow, the system works slowly; if the oscillation is fast, the system works quickly (but power consumption also increases).

A. Oscillation Period: The oscillation beat of the oscillation source. B. Machine Cycle: The number of oscillation cycles (beats) required for the microcontroller to complete a basic operation. C. Instruction Cycle: The number of machine cycles required to execute an instruction. Different instructions require different numbers of machine cycles.

5. Basic Concepts of ARM Architecture

(1) ARM: Advanced RISC Machine.

(2) The ARM architecture supports two instruction sets: ARM instruction set and Thumb instruction set.

(3) The ARM core has four functional modules:

A. T Module: Represents 16-bit Thumb, which reduces code size while maintaining performance. B. D Module: Represents Debug, with structures for debugging typically including a boundary scan chain JTAG. C. M Module: Represents 8-bit multiplier. D. I Module: Represents EmbeddedICE Logic, used for real-time breakpoint observation and variable observation logic circuit part.

(4) The ARM processor has seven operating modes:

A. User Mode: Normal program execution mode for application programs. B. Fast Interrupt Mode (FIQ): For fast interrupt handling, used for high-speed data transfer and channel processing. C. External Interrupt Mode (IRQ): For general interrupt handling. D. Supervisor Mode (SVE): A protected mode for the operating system. E. Data Access Abort Mode (Abort): For virtual storage and storage protection. F. Undefined Instruction Abort Mode (Undefined): Entered when an undefined instruction is executed. G. System Mode: For running privileged operating system tasks.

All modes except User Mode are called privileged modes; in these modes, programs can access all system resources and can switch processor modes arbitrarily. Among these, except for System Mode, the other five privileged modes are also called exception modes. Processor modes can be switched through software control or through external interrupts or exception handling processes. Most user programs run in User Mode, where application programs cannot access some system resources protected by the operating system and cannot directly switch processor modes. When a processor mode switch is needed, the application can cause an exception handling process to switch the processor mode. This architecture allows the operating system to control all system resources. When an application program experiences an exception interrupt, the processor enters the corresponding exception mode. Each exception mode has a set of registers for the corresponding exception handler to use, ensuring that the registers in User Mode are not damaged when entering an exception mode. System Mode is not entered through an exception process; it has exactly the same registers as User Mode, but belongs to a privileged mode, can access all system resources, and can directly switch processor modes, primarily for operating system tasks.

(5) The ARM processor has a total of 37 registers: 31 general-purpose registers and 6 status registers.

A. General-purpose registers include R0~R15, which can be divided into three types:

a. Unbanked Registers R0~R7: In all processor modes, unbanked registers point to the same physical register.

b. Banked Registers R8~R14: For R8~R12, each register corresponds to two different physical registers, and the physical register accessed each time depends on the current processor running mode. For R13 and R14, each register corresponds to six different physical registers, one of which is shared between User Mode and System Mode. R13 is commonly used as the stack pointer in ARM instructions. Since each running mode of the processor has its own independent physical register R13, it is generally necessary to initialize R13 for each mode during the initialization part of user application programs to point to the stack space for that running mode. R14, also known as the Link Register (LR), has two special functions in the ARM architecture: storing the return address of the current subroutine when a subroutine is called via the BL or BLX instruction; storing the address to return to when an exception interrupt occurs.

c. Program Counter R15 (PC).

Due to the pipelining mechanism in ARM, when the PC value is correctly read, it is the current instruction address value plus 8 bytes. In other words, the PC points to the address of the next two instructions. In ARM instruction state, the 0 and 1 bits of the PC are 0; in Thumb instruction state, the 0 bit of the PC is 0.

B. Program Status Register

a. The ARM architecture includes one current program status register (CPSR) and five banked program status registers (SPSR), which can be set and read using MSR and MRS instructions.

b. Current Program Status Register CPSR: Stores information about the current processor state and can be accessed in any processor mode.

c. Banked Program Status Register SPSR: Each exception handling mode has a dedicated physical status register. When a specific exception interrupt occurs, this register stores the content of the current program status register CPSR, allowing recovery of CPSR using the value saved in SPSR when exiting the exception interrupt program.

d. Since User Mode and System Mode are not exception modes, they do not have SPSR. Accessing SPSR in these two modes yields unknown results.

(6) Addressing Modes of ARM Instructions

The addressing mode refers to the method by which the processor finds the physical address based on the address information provided in the instruction.

A. Immediate Addressing: The operand is provided directly in the instruction, allowing retrieval of the operand when the instruction is fetched. ADD R0, R0, #1; R0=R0+1

B. Register Addressing: Using the value in a register as the operand. ADD R0, R1, R2; R0=R1+R2

C. Register Indirect Addressing: Using the value in a register as the address of the operand, which is stored in memory. ADD R0, R1, [R2]; R0=R1+[R2] LDR R0, [R1]; R0=[R1] STR R0, [R1]; [R1]=R0

D. Base-Offset Addressing: Adding the content of a register (usually referred to as the base register) to an address offset provided in the instruction to obtain an effective address for the operand. LDR R0, [R1, #4]; R0=[R1+4] LDR R0, [R1, #4]!; R0=[R1+4] R1=R1+4 LDR R0, [R1], #4; R0=[R1] R1=R1+4 LDR R0, [R1, R2]!; R0=[R1+R2]

E. Multiple Register Addressing: One instruction can transfer multiple register values. LDMIA R0, {R1, R2, R3}; R1=[R0] R2=[R0+4] R3=[R0+8]

F. Relative Addressing: Using the current value of the program counter PC as the base address, with the address label in the instruction as the offset, both added together to obtain the effective address of the operand.

BL NEXT; Jump to execute subroutine NEXT… NEXT… MOV PC, LR; Return from subroutine

G. Stack Addressing: Supports four types of stack operations:

a. Full Incrementing Stack: The stack pointer points to the last data pushed, growing from low address to high address. b. Full Decrementing Stack: The stack pointer points to the last data pushed, growing from high address to low address. c. Empty Incrementing Stack: The stack pointer points to the next empty location where data will be placed, growing from low address to high address. d. Empty Decrementing Stack: The stack pointer points to the next empty location where data will be placed, growing from high address to low address.

(7) Storage Methods in ARM

A. Big Endian: The high byte of data is stored at a low address, and the low byte is stored at a high address. B. Little Endian: The low byte of data is stored at a low address, and the high byte is stored at a high address.

(8) ARM Interrupts and Exceptions

A. The ARM core supports seven types of interrupts, with different interrupts operating in different handling modes and having different priorities, and each interrupt has a fixed interrupt address entry. When an interrupt occurs, the corresponding R14 (LR) stores the interrupt return address, and SPSR stores the value of the current program status register CPSR.

B. Since the ARM core supports pipelined operation, the address stored in the LR register may point to the address of the instruction following the interrupt, so after completing different interrupt handling, the LR register value must be processed before writing to the P15 (PC) register.

C. Specific meanings of ARM exceptions:

a. Reset: When the reset level of the processor is valid, a reset exception occurs, and the program jumps to the exception reset handling program for execution.

b. Undefined Instruction: When the ARM processor or coprocessor encounters an instruction that cannot be processed, an undefined instruction exception occurs. This exception mechanism can be used for software simulation.

c. Software Interrupt: This exception is generated by executing the SWI instruction and can be used for privileged operation instructions in user mode. This exception mechanism can implement operating system call functionality.

d. Instruction Prefetch Abort: If the address of the instruction being prefetched does not exist or is not accessible by the current instruction, the memory sends an abort signal to the processor; however, the instruction prefetch abort exception occurs only when the prefetched instruction is executed.

e. Data Access Abort: If the target address of the processor’s data access instruction does not exist or is not accessible by the current instruction, the processor generates a data access abort exception.

f. External Interrupt Request: When the ARM external interrupt request pin is valid, and the I bit in CPSR is 0, an IRQ exception occurs. The system’s peripheral devices can request interrupt service through this exception.

g. Fast Interrupt Request: When the ARM fast interrupt request pin is valid, and the F bit in CPSR is 0, an FIQ exception occurs.

D. Response process of the ARM processor to exception interrupts:

a. Store the address of the next instruction in the corresponding link register LR. b. Copy CPSR to the corresponding SPSR. c. Depending on the type of exception, forcibly set the CPSR’s mode bits. d. Forcibly fetch the next instruction from the relevant exception vector address, jumping to the corresponding exception handling program.

E. Returning from the ARM processor’s exception interrupt handling program:

a. Restore the processor state of the interrupted program, copying SPSR to CPSR. b. If the interrupt was disabled when entering exception handling, it must be cleared here. c. The value in the link register LR is subtracted by the corresponding offset and sent to PC.

F. The reset exception interrupt handler does not need to return. The reset exception interrupt program begins execution of the entire user program.

Source: Chen Zhou Side Boat

http://www.cnblogs.com/chenshikun/p/7722872.html

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